HCS08 FAMILY

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Each MCU device in the HCS08 Family consists of the HCS08 core plus several memory and peripheral modules. The HCS08 core consists of:

	HCS08 CPU
	Background debug controller (BDC)
	Support for up to 32 interrupt/reset sources
	Chip-level address decode

The HCS08 CPU executes all HC08 instructions, as well as a background (BGND) instruction and additional addressing modes on the LDHX, STHX, and CPHX instructions to improve compiler efficiency.

The maximum clock speed for the CPU is 40 MHz (typically generated from a crystal or internal clock generator). The CPU performs operations at this 40 MHz rate and the maximum bus rate is 20 MHz (half the CPU clock frequency).

The background debug controller (BDC) is built into the CPU core to allow easier access to address generation circuits and CPU register information. The BDC includes one hardware breakpoint. Other more sophisticated breakpoints are normally included in the separate on-chip debug module. The BDC allows access to internal register and memory locations via a single pin on the MCU.

Features:

	4K–60K byte FLASH or ROM memory
	128–4K byte Static RAM
	Clock generation modules

– Full-featured internal clock generator (ICG) capable of operation with no external components (frequency multiplication is accomplished with a frequency-locked loop (FLL) that does not use any external filter components)

– Traditional Pierce oscillator with no FLL or PLL (OSC)

	Debug module with nine trigger modes and bus capture FIFO (DBG)
	Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module)
	Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints.
	Support for up to 32 interrupt/reset sources
	Power-saving modes: wait plus three stops
	System protection features:

– Optional computer operating properly (COP) reset

– Low-voltage detection with reset or interrupt

– Illegal opcode detection with reset

– Illegal address detection with reset (some devices don’t have

illegal addresses)

	8-channel, 10-bit analog-to-digital converter (ATD)
	Two serial communications interface modules (SCI)
	Serial peripheral interface module (SPI)
	Clock source options include crystal, resonator, external clock or internally generated clock with precision NVM trimming
	Inter-integrated circuit bus module to operate up to 100 kbps (IIC)
	One 3-channel and one 5-channel 16-bit timer/pulse width modulator (TPM) modules with selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centeredPWM (CPWM) on all channels (TPMx).

	8-pin keyboard interrupt module (KBI)
	16 high-current pins (limited by package dissipation)
	Software selectable pullups on ports when used as input. Selection is on an individual port bit basis. During output mode, pullups are disengaged.
	Internal pullup on RESET and IRQ pin to reduce customer system cost